AMD RYZEN

[JurajSlovakID]

Kedy pride 3rd generacia RYZENu?

[Leon]

AMD Zen 2 – More Than Just a Frequency / IPC Bump

https://wccftech.com/amd-zen-2-ryzen-ep ... pc-clocks/

Most people think that Zen 2 is nothing more than a generational Frequency / IPC bump. That is a very wrong assumption as Zen 2 as an architecture is entirely overhauled. The jump from Zen to Zen+ was one incremental step, the jump from Zen+ to Zen 2 aims to be a revolutionary step.

[M1ch4l]

Uz vieme cas toho eventu? Zatial som to nikde nevidel...

[maniak]

V rozmedzi od 6.00 do 18.00 nasho casu.

[loleqboleq]

Čožžžééé? To dnes bude? Idem robiť pukance.

[Leon]

Uz vieme cas toho eventu? Zatial som to nikde nevidel...

ak počítam správne tak na anadtechu o 15:00 bude liveblog

https://twitter.com/IanCutress/status/1 ... 7238506497

[M1ch4l]

Anandtech na stranke pisu 9am pacific, takze u nas by to malo byt 18:00

[Leon]

jj išiel som to teraz editnúť. Vtedy to tam ešte nebolo, vychádzal som z twitteru a tam mal ešte len predpokladaný čas. Každopádne ryzen3000 dnes asi neuvidíme. ale aspoň budeme vedie čo za arch to je.

[M1ch4l]

No tak zatial sa potvrdilo len to oddelenie jadier do 7nm chipletov a centralny 14nm ciplet. Okrem ineho pre Epyc podpora PCIe 4.0.

Zatial nic nejak mega konkretne, o Vege MI60 toho padlo viac. Ta je inak celkom drsna, ale najlepsie na tom su tie spravy o software.

[Leon]

No je toho strašne veľa

Major Node, Significant Investment
Faster, Smaller, Lower Power Transistors (2x Density, 0.5x Power, 1.25x Performance at same performance/power)
Multiple Products in Development
Deep Partnership with TSMC and Design Automation Vendors
AMD has made significant changes to their CPU architecture which help deliver twice the throughput of their first generation Zen architecture. The major points include an entirely redesigned execution pipeline, major floating point advances with doubled the floating point to 256-bit and double bandwidth for load/store units. One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX) which will now be risen to 8 per CCX compared to 4 per CCX.

Improved Execution Pipeline
Doubled Floating Point (256-bit) and Load/Store (Doubled Bandwidth)
Doubled Core Density
Half the Energy Per Operation
Improved Branch Prediction
Better Instruction Pre-Fetching
Re-Optimized Instruction Cache
Larger Op Cache
Increased Dispatch / Retire Bandwidth
Maintaining High Throughput for All Modes

Vzhledem ke zmenam si troufam tvrdit, ze to porazi 9900k jak nic a bude to zrat pulku co 9900k.

[mino_85]

Ešte si počkáme, ale bodaj by.

[M1ch4l]

Tak keby 7nm procesor neporazil 14nm, bolo by to velmi biedne. Znie to dobre, ale primarne je to o tej skalovatelnosti.

Budu samostatne vyrabat velke mnozstvo 7nm core chipletov a aspon 3 verzie 14nm I/O chipletov. Jednu pre mainstream, jednu pre HEDT, a jednu pre servery. Mozno APU budu tiez potrebovat vlastny I/O chiplet, ale skor nie. Zvacsenie CCX na 8 jadier dava zmysel, pretoze I/O chiplet sa napaja priamo na CCX.

Takto keby chceli, mohli by dat 16 jadier aj do AM4. Pre AM4 si od zaciaktu mozu navrhnut a vyrabat I/O chiplet s dvoma CCX pripojeniami a vyuzivat len jedno. Potom pre APU na to 2. napoja GPU, alebo mozu pridat druhe CCX a zvysit pocet jadier. Teoreticky by aj kazdy AM4 procesor mohol mat nejake zobrazovadlo. Ta flexibilita, ktoru im ponuka to I/O die, to je brutalne.

Viem si predstavit este dalej v buducnosti ako IF je uplne univerzalny interconnect a k jednemu I/O die sa daju pripajat rozne typy chipletov.

[CageJ]

AMD je momentalne tech. lider ... Intel zaspal.

[Zoltan Balaton]

https://www.cnews.cz/amd-procesory-cpu- ... e-servery/

[M1ch4l]

AMD je momentalne tech. lider ... Intel zaspal.

Veru, Intel zaspal. Predpokladam, ze nikto z vedenia Intelu nejak uz nepocital s konkurenciou od AMD, takze Ryzen ich musel poriadne zaskocit. Este prejde nejaky cas, nez na to budu schopni realne zareagovat. Potrebuju totiz novu architekturu, AMD presunulo hru na iny level.

Je mi smutno ked sa zmyslim nad tym, kde by sme mohli byt, keby Intel nespal a nevyciciaval 10 rokov 4-jadra.

==============

Na Guru3D maju peknu fotku, takmer kolmo na procak https://www.guru3d.com/news-story/amd-z ... close.html

Tak som si vygooglil, ze ten SP3/TR4 package ma rozmery 71.9 x 58.5mm
Spocitanim pixelov a drobnym prepoctom som napocital:
Core-die je zhruba 7.1mm x 10.2mm, velkost vychadza na necelych 73mm^2.
I/O die je zhruba 14.8mm x 28.3mm, velkost necelych 420mm^2.

Dohromady 8x73 + 420 = 1004. Je to brutal, vyrobit to ako monoliticky cip je prakticky nemozne. Tu je vlastne ta brutalna sila tohto pristupu. Je to "zlepenec" mensich kuskov, ktore sa v pohode daju vyrabat, ale sucet velkosti cipov je nad hranicou toho, co by sa rozumne dalo vyrabat.

edit2:

Po prepocte so Zen 1 som este spocital, ze z 213mm^2 maju vsetky non-core casti necelych 117mm^2. Takze velkost I/O die zhruba sedi na 4-nasobok toho, co asi sedi na ocakavania, a teda sa asi nekona ziadna L4 cache vnutri I/O die.