4 jadrove CPU - pristup do pamate

[LoPiO]

Mam taku otazku ako je to s pristupom do pamate napriklad pripravovaneho core 2 quad Nebudu sa dve jadra byt o pristup do jednej pamate ked budeme mat dual channel Ake bude spomalenie

P.S: Ano googlovat sa mi nechce

[beardie]

biju sa teraz o pristup do pamate Smithfieldy a Preslery?

[Panoramix0903]

Intel Smart Memory Access improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses. The goal is to ensure that data can be used as quickly as possible and that this data is located as close as possible to where it’s needed to minimize latency and thus improve efficiency and speed. Intel Smart Memory Access includes an important new capability called memory disambiguation, which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute BEFORE all previous store instructions are executed. To understand how this works, we have to look at what happens in most out-of-order microprocessors. Normally when an out-of-order microprocessor reorders instructions, it can’t reschedule loads ahead of stores because it doesn’t know if there are any data location dependencies it might be violating. Yet in many cases, loads don’t depend on a previous store and really could be loaded before, thus improving efficiency. The problem is identifying which loads are okay to load and which aren’t. Intel's memory disambiguation uses special intelligent algorithms to evaluate whether or not a load can be executed ahead of a preceding store. If it intelligently speculates that it can, then the load instructions can be scheduled before the store instructions to enable the highest possible instruction-level parallelism. If the speculative load ends up being valid, the processor spends less time waiting and more time processing, resulting in faster execution and more efficient use of processor resources. In the rare event that the load is invalid, Intel’s memory disambiguation has built-in intelligence to detect the conflict, reload the correct data and re-execute the instruction. In addition to memory disambiguation, Intel Smart Memory Access includes advanced prefetchers. Prefetchers do just that—“prefetch” memory contents before they are requested so they can be placed in cache and then readily accessed when needed. Increasing the number of loads that occur from cache versus main memory reduces memory latency and improves performance. To ensure data is where each execution core needs it, the Intel Core microarchitecture uses two prefetchers per L1 cache and two prefetchers per L2 cache. These prefetchers detect multiple streaming and strided access patterns simultaneously. This enables them to ready data in the L1 cache for “just-in-time” execution. The prefetchers for the L2 cache analyze accesses from cores to ensure that the L2 cache holds the data the cores may need in the future. Combined, the advanced prefetchers and the memory disambiguation result in improved
execution throughput by maximizing the available system-bus bandwidth and hiding latency to the memory subsystem.

[Gudas]

mno, spomalenie dufam asi nebude: http://anandtech.com/cpuchipsets/showdo ... i=2846&p=2