Technicke udaje:
( 1 ) Single-core new micro-architecture
( 2 ) 1.8 GHz to 0.8GHz
( 3 ) 32 KB (instruction) +24 KB (data) L1 cache
( 4 ) 512 KB L2 cache 8-Way
( 5 ) Hyper-Threading (HT) technology (1 core / 2 threads)
( 6 ) Intel64/SSSE3/VT/XD
( 7 ) 400/533 MHz FSB support
( 8 ) 441-pin package FCBGA8
Verzie:
Zdroj
Intel Silverthorne mobile chip to be slower than expected ?
Luckily, the folks at Ars Technica—with the help of David Kanter from Real World Technologies—were able to unearth some additional information about Silverthorne's design in the program for the 2008 International Solid State Circuits Conference. The information says Silverthorne will have a two-issue, in-order pipeline with integer and floating point execution units, 32KB of iL1 cache, 24KB of dL1 cache, 512KB of L2 cache, and a 533MT/s front-side bus.
According to Ars, that suggests the chip harbors a design similar to that of the original Pentium processor, which was also a two-issue, in-order chip. Based on this find, the site extrapolates that Silverthorne will be at a performance and power efficiency disadvantage compared to RISC embedded processors from the likes of ARM [...]
Zdroj + viac technickych detailov