PCI Express 3.0

[yesper]

V novembri by mali byt konecne zname oficialne specifikacie od PCI-SIGu pre PCI Express 3.0, doposial boli zverejnene vo verzii 0.9. Prve gpus sa zvycajne objavuju az po roku od oznamenia finalnych spec., teda asi najskor v Q2/11.

SAN FRANCISCO, Calif. – The base specification for PCI Express 3.0 should be complete by November, opening the door to a flow of products for the fast interconnect in 2011.

The PCI Special Interest Group released in mid-August a version 0.9 of the spec for the link that has a maximum data rate of 8 GigaTransfers/second. After a 60 day review it expects to release a final version of the base spec.

Typically, products are generally available for a new version of PCI Express about a year after the spec becomes final, said Al Yanes, chairman of the PCI SIG. However, some companies hungry for more bandwidth will roll products early next year.

Mellanox Technologies expects to release before June a version of its 40 Gbit Infiniband adapters using PCIe 3.0. The adapters now ride the PCI Express Gen 2 bus, but the 5 GTransfers/s link is a bottleneck that throttles throughput of the Mellanox cards down to 26 Gbits/s.

One source said Intel will support PCIe 3.0 natively on future versions of its Sandy Bridge processors geared for servers. Those chips could ship before the end of 2011. Initial Sandy Bridge CPUs shipping before April build in PCIe Gen 2.

The new interconnect is expected to be used for four-port 10 Gbit/'s Ethernet chips and next-generation 40 Gbit Ethernet chips now coming to market. It also will be used for high-end graphics cards and solid-state drives.

The PCI SIG does not expect to complete a specification for testing PCIe Gen 3 products until late next year. The group will issue tools to validate designs and start interoperability workshops in the middle of 2011.

The fast interconnect faced delays, in part due to the complexity of delivering an 8 GTransfer technology that could be broadly deployed by cost-constrained PCs. The spec uses dynamic feedback equalization which requires relatively sophisticated design techniques to maintain signal integrity.

http://www.eetimes.com/electronics-news ... n-November

[stefan222]

nieco nove?

[crux2005]

PCI-Express 3.0 je uzatvorená kapitola pre túto sekciu - nejedná sa už o žiadne špekulácie.

lock